1. Field of the Invention
The present invention relates to a port sampling circuit apparatus performing sampling of input ports of a microcomputer based on conditions instructed by a central processing unit, and also relates to a microcomputer incorporating this port sampling circuit apparatus.
2. Description of the Background Art
A central processing unit (hereinafter referred to as CPU), constituting an essential part of a microcomputer, is often required to have the capability of sampling the level of a signal produced from an external device or the like, which is connected to an input terminal of the microcomputer, for the purpose of changing the control condition thereof. In such a case, a control program of the CPU needs to be described so as to realize this function. According to this control program, the CPU performs sampling of the input ports of the microcomputer at predetermined intervals (e.g., at intervals of several tens xcexc seconds to several hundreds xcexc seconds).
More specifically, the CPU performs a writing operation to output a timing signal for latching the data entered into the input port of the microcomputer. Then, the CPU performs a reading operation to read out the latched data. The CPU periodically repeats these write and read operations.
Hence, a definitely necessary process is for creating or producing the software for realizing the above-described sampling operation. Furthermore, in actual operations of the CPU, the control program needs to absorb the burden of such sampling operations. Accordingly, in the even that the CPU has many other tasks to be performed, it is difficult to shorten the sampling period sufficiently.
In view of the foregoing problem of the prior art, the present invention has an object to provide a port sampling circuit apparatus which is capable of reducing the burden of CPU even when the sampling operation is repetitively performed.
Furthermore, the present invention has an object to provide a microcomputer incorporating this port sampling circuit apparatus.
To accomplish the above and other related objects, the present invention provides a port sampling circuit apparatus including a hardware arrangement for automatically performing sampling of data given to an input port of a microcomputer based on conditions instructed by a central processing unit and for storing the sampled data into a data register whose stored data is readable by the central processing unit.
According to this arrangement, the CPU needs not to perform periodical sampling of input ports of the microcomputer. The required thing for the CPU is only reading out the data at appropriate timings when any data is given to its input ports of the microcomputer from the external devices.
Accordingly, there is no necessity of adding the programmatic description relating to the sampling processing into the control program of the CPU. The process of creating the program of the CPU can be simplified. Furthermore, the processing burden of the CPU in the actual operations can be also reduced.
Furthermore, according to a preferable embodiment of the present invention, the hardware arrangement of the port sampling circuit apparatus includes a sampling period setting register for setting a sampling period, a sampling timing signal output section for outputting a sampling timing signal periodically based on the sampling period being set by the sampling period setting register, and a data latch section for latching the data given to the input port of the microcomputer based on the sampling timing signal produced from the sampling timing signal output section and for storing the latched data into the data register.
According to this arrangement, the sampling period can be adequately changed when the CPU instructs the setting data to the sampling period setting register. The sampling timing signal output section periodically generates the sampling timing signal based on the sampling period being thus instructed by the CPU, and the data latch section latches the data given to the input port of the microcomputer based on the sampling timing signal and stores the latched data into the data register. Thus, the sampling period can be arbitrarily changed or adjusted according to practical specifications of individual applications.
Furthermore, according to the preferable embodiment of the present invention, the hardware arrangement of the port sampling circuit apparatus includes an output condition changing means for periodically changing a condition of an output port of the microcomputer in synchronism with timing of the sampling. For example, the hardware arrangement of the port sampling circuit apparatus includes an output condition changing means for periodically changing the condition of an output port of the microcomputer in synchronism with the sampling timing signal.
In some cases, in performing sampling of the input ports, it may be necessary to change the conditions of peripheral circuits of the microcomputer.
For example, depending on the type of external devices, or depending on the arrangement of peripheral circuits, outputting signals to the input ports is feasible only when the CPU is in an active condition.
Accordingly, in such a case, according to the above arrangement, the port sampling circuit arrangement automatically changes the condition of the output port and periodically drives the external device connected to the output port in synchronism with the sampling timing. Hence, the CPU needs not to perform the driving control of the external devices. The processing burden of the CPU can be further reduced.
Furthermore, according to the preferable embodiment of the present invention, the output condition changing means includes a condition change period setting register for setting a period for changing the condition of the output port, a condition change timing signal output section for periodically outputting a condition change timing signal based on the condition change period being set by the condition change period setting register, and a condition changing section for changing the condition of the output port based on the condition change timing signal produced from the condition change timing signal output section. According to this arrangement, the CPU can arbitrarily store the period for changing the condition of the output port to the condition change period setting register.
Furthermore, according to the preferable embodiment of the present invention, the condition change period setting register is also able to serve as the sampling period setting register. This is effective to perform both of settings by using only one register. The setting processing can be simplified.
Furthermore, according to the preferable embodiment of the present invention, the hardware arrangement of the port sampling circuit apparatus further includes a sampling start time setting register for setting a time required after the condition of the output port changes until the sampling of data given to the input port starts, and the sampling timing signal output section is constituted so as to periodically output the sampling timing signal based on the sampling period and also based on the sampling start time being set by the sampling start time setting register.
According to this arrangement, in the case that the condition of the output port is changed to drive the external device, it becomes possible to set optimum sampling timing for individual cases so that the data level of the data entered to the input port from the external device is sufficiently stabilized after starting the driving of this device.
Furthermore, according to the preferable embodiment of the present invention, the hardware arrangement of the port sampling circuit apparatus further includes an expected value set register into which an expected value of sampling data is set by the central processing unit, and a coincidence signal output section for outputting a coincidence signal to the outside when the data latched by the data latch section agrees with the expected value being set in the expected value set register.
Namely, when the expected value is set beforehand in the expected value set register, the port sampling circuit apparatus can cancel the power saving mode as soon as it samples the data identical with the expected value. Hence, the CPU needs not to perform the polling for the input ports at predetermined intervals to check whether or not the sampled data is equal to the expected value. Accordingly, the processing burden of CPU can be reduced effectively.
Another aspect of the present invention provides a microcomputer including a central processing unit and the above-described port sampling circuit apparatus. According to this arrangement, it becomes possible to leave all of the sampling processing to the port sampling circuit apparatus so as to increase the processing capability of the CPU for the remaining tasks.
According to the preferred embodiment of the present invention, the coincidence signal is supplied as an interrupt signal to the central processing unit. Thus, the CPU can immediately know the fact that the data identical with the expected value has been sampled.
Furthermore, according to the preferred embodiment of the present invention, the central processing unit has a function of executing a power saving mode for reducing electric power consumption according to which the central processing unit is brought into a low-power or less-activated condition. The coincidence signal is supplied to the central processing unit as a cancel signal for canceling the power saving mode.
For example, in the event that the CPU judges that there is no necessity of continuing ordinary operations, it is preferable to change the operating mode of the CPU into the power saving mode, for example, by stopping supply of the clock signal. In general, the CPU cannot perform the sampling of the input ports in the power saving mode. On the contrary, when the CPU needs to perform the sampling operation periodically, the CPU could not go into the power saving mode.
In view of the above, it is preferable that the CPU sets the expected value beforehand in the expected value set register. During the power saving mode of the CPU, the port sampling circuit apparatus continuously performs the sampling processing and cancels the power saving mode as soon as the data identical with the expected value is sampled.
Accordingly, the CPU can easily go into the power saving mode in the event that the next processing should start in response to the sampling of specific data. The required thing for the CPU is only waiting for the cancel signal (i.e., coincidence signal) which is issued by the port sampling circuit apparatus. Therefore, the CPU does not fail to catch the data incoming during the power saving mode and can respond to it or behave properly. In other words, the CPU can effectively utilize the power saving mode. Electric power consumption can be reduced satisfactorily.